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MC10EP446, MC100EP446 3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter
Description
The MC10/100EP446 is an integrated 8-bit parallel to serial data converter. The device is designed with unique circuit topology to operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence from parallel data into a serial data stream is from bit D0 to D7. The parallel input pins D0-D7 are configurable to be threshold controlled by CMOS, ECL, or TTL level signals. The serial data rate output can be selected at internal clock data rate or twice the internal clock data rate using the CKSEL pin. Control pins are provided to reset (SYNC) and disable internal clock circuitry (CKEN). In either CKSEL modes, the internal flip-flops are triggered on the rising edge for CLK and the multiplexers are switched on the falling edge of CLK, therefore, all associated specification limits are referenced to the negative edge of the clock input. Additionally, VBB pin is provided for single-ended input condition. The 100 Series devices contain temperature compensation network.
Features
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MARKING DIAGRAMS*
MCxxx EP446 AWLYYWWG LQFP-32 FA SUFFIX CASE 873A
1
* * * * * * * * * *
3.2 Gb/s Typical Data Rate Capability Differential Clock and Serial Outputs VBB Output for Single-ended Input Applications Asynchronous Data Reset (SYNC) PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs Parallel Interface Can Support PECL, TTL or CMOS Pb-Free Packages are Available*
1
32
QFN32 MN SUFFIX CASE 488AM
MCxxx EP446 AWLYYWWG G
xxx = 10 or 100 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2007
February, 2007 - Rev. 9
1
Publication Order Number: MC10EP446/D
MC10EP446, MC100EP446
D0 D1 D2 D3 D4 D5 D6 D7
D2
D5
D0
D1
D3
D4
D6
18
24
23
22
21
20
19
24 VCC VCF VEF VEE SYNC SYNC VBB2 VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 VEE PCLK PCLK VCC
VCC VCF VEF VEE
D7
17 16 15 14 13 12 11 10 9
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
VEE PCLK PCLK VCC SOUT SOUT VCC VCC
MC10EP446 MC100EP446
13 12 11 10 9
Exposed Pad (EP)
SOUT SYNC SOUT SYNC VCC VCC VBB2 VCC
2
3
4
5
6
7
8
CKEN
CKEN
CLK
CLK
CKEN
CKEN
CLK
CLK
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
CKSEL
VBB1
VCC
VEE
Figure 1. LQFP-32 Pinout (Top View)
Figure 2. QFN-32 Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN D0*-D7* SOUT, SOUT CLK*, CLK* PCLK, PCLK SYNC*, SYNC** CKSEL* CKEN*, CKEN* VCF VEF VBB1, VBB2 VCC VEE ECL, CMOS, or TTL Parallel Data Input ECL Differential Serial Data Output ECL Differential Clock Input ECL Differential Parallel Clock Output ECL Conversion Synchronizing Differential Input (Reset)*** ECL Clock Input Selector ECL Clock Enable Differential Input ECL, CMOS, or TTL Input Selector ECL Reference Mode Connection Reference Voltage Output Positive Supply Negative Supply FUNCTION
* Pins will default LOW when left open. **Pins will default HIGH when left open. ***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates the conversion process synchronously on the next rising edge of CLK.
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2
CKSEL
VBB1
VCC
VEE
MC10EP446, MC100EP446
Table 2. TRUTH TABLE
Function Pin CKSEL SOUT: PCLK = 8:1 CLK: SOUT = 1:1 CLK SOUT CKEN SYNC Synchronously Disables Normal Parallel to Serial Conversion Asynchronously Resets Internal Flip-Flops* HIGH SOUT: PCLK = 8:1 CLK: SOUT = 1:2 CLK SOUT Synchronously Enables Normal Parallel to Serial Conversion Synchronous Enable LOW
*The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates the conversion process synchronously on the next rising edge of CLK.
Table 3. INPUT VOLTAGE LEVEL SELECTION TABLE
Input Function ECL Mode CMOS Mode TTL Mode* Connect To VCF Pin VEF Pin No Connect 1.5 V $ 100 mV
Table 4. DATA INPUT OPERATING VOLTAGE TABLE
Power Supply (VCC,VEE) PECL NECL Data Inputs (D [0:7]) CMOS p N/A TTL p N/A PECL p N/A NECL N/A p
*For TTL Mode, if no external voltage can be provided, the reference voltage can be provided by connecting the appropriate resistor between VCF and VEE pins.
Power Supply 3.3 V 5.0 V
Resistor Value 10% (Tolerance) 1.5 kW 500 W
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MC10EP446, MC100EP446
D0 D CR Q MUX 2:1 Q D CR Q
D4
D CR
MUX 2:1 Q MUX 2:1 Q D CR Q
D CR
Q
D2
D CR
D6
D CR
MUX 2:1 Q MUX 2:1 Q D CR Q
SOUT SOUT
D1
D CR
D5
D CR
MUX 2:1 Q MUX 2:1 Q D CR Q
D CR
Q
D3
D CR
D7
D CR
/2
/2 PCLK PCLK
/2 CKEN CKEN CLK CLK CKSEL SYNC VCC VEE SYNC VBB VCF VEF D CR Q
MUX 2:1
Control Logic
Figure 3. Logic Diagram
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MC10EP446, MC100EP446
Table 5. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 2 - Value 75 kW 37.5 kW > 2 kV > 100 V > 2 kV Pb-Free Pkg Level 2 Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP-32 QFN-32 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 962 Devices
Table 6. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 2S2P <2 to 3 sec @ 248C <2 to 3 sec @ 260C LQFP-32 LQFP-32 LQFP-32 QFN-32 QFN-32 QFN-32 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 31 27 12 265 265 Unit V V V mA mA C C C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC10EP446, MC100EP446
Table 7. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) CMOS PECL TTL Input LOW Voltage (Single-Ended) CMOS PECL TTL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current (All Except SYNC, SYNC) SYNC, SYNC 0.5 -150 0 1365 0 1790 2.0 1840 800 1690 800 1990 3.3 150 0.5 0.5 -150 0 1460 0 1855 2.0 1905 800 1755 800 2055 3.3 150 0.5 0.5 -150 0 1490 0 1915 2.0 1965 800 1815 800 2115 3.3 150 0.5 2000 2090 2000 3300 3300 3300 2000 2155 2000 3300 3300 3300 2000 2215 2000 3300 3300 3300 Min 90 2165 1365 Typ 110 2290 1490 Max 140 2415 1615 Min 90 2230 1430 25C Typ 110 2355 1555 Max 140 2480 1680 Min 95 2290 1490 85C Typ 115 2415 1615 Max 145 2540 1740 Unit mA mV mV mV
VIL
mV
VBB VIHCMR IIH IIL
mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 3. All loading with 50 W to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP446, MC100EP446
Table 8. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40C Symbol IEE VOH VOL VIH Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) CMOS PECL TTL Input LOW Voltage (Single-Ended) CMOS PECL TTL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) Input HIGH Current Input LOW Current (All Except SYNC, SYNC) SYNC, SYNC 0.5 -150 0 3065 0 3490 2.0 3540 1500 3390 800 3690 5.0 150 0.5 0.5 -150 0 3130 0 3555 2.0 3605 1500 3455 800 3755 5.0 150 0.5 0.5 -150 0 3190 0 3615 2.0 3665 1500 3915 800 3815 5.0 150 0.5 3500 3790 2000 5000 5000 5000 3500 3855 2000 5000 5000 5000 3500 3915 2000 5000 5000 5000 Min 90 3865 3065 Typ 110 3950 3190 Max 140 4115 3315 Min 90 3930 3130 25C Typ 110 4055 3255 Max 140 4180 3380 Min 95 3990 3190 85C Typ 115 4115 3315 Max 145 4240 3440 Unit mA mV mV mV
VIL
mV
VBB VIHCMR IIH IIL
mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 6. All loading with 50 W to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP446, MC100EP446
Table 9. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 8)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Input HIGH Current Input LOW Current (All Except SYNC, SYNC) SYNC, SYNC 0.5 -150 Min 90 -1135 -1935 -1210 -1935 -1510 -1460 Typ 110 -1010 -1810 Max 140 -885 -1685 -885 -1610 -1310 0.0 Min 90 -1070 -1870 -1145 -1870 -1445 -1395 25C Typ 110 -945 -1745 Max 140 -820 -1620 -820 -1545 -1245 0.0 Min 95 -1010 -1810 -1085 -1810 -1385 -1335 85C Typ 115 -885 -1685 Max 145 -760 -1560 -760 -1485 -1185 0.0 Unit mA mV mV mV mV mV V
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 W to VCC - 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 10. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)
-40C Symbol IEE VOH VOL VIH Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) CMOS PECL TTL Input LOW Voltage (Single-Ended) CMOS PECL TTL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) Input HIGH Current Input LOW Current 0.5 Min 90 2155 1355 2000 2075 2000 0 1355 0 1775 2.0 1875 Typ 110 2280 1480 Max 130 2405 1605 3300 3300 3300 800 1675 800 1975 3.3 Min 90 2155 1355 2000 2075 2000 0 1355 0 1775 2.0 1875 25C Typ 110 2280 1480 Max 130 2405 1605 3300 3300 3300 800 1675 800 1975 3.3 Min 95 2155 1355 2000 2075 2000 0 1355 0 1775 2.0 1875 85C Typ 115 2280 1480 Max 135 2405 1605 3300 3300 3300 800 1675 800 1975 3.3 Unit mA mV mV mV
VIL
mV
VBB VIHCMR
mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 12. All loading with 50 W to VCC - 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP446, MC100EP446
Table 11. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)
-40C Symbol IEE VOH VOL VIH Characteristic Power Supply Current Output HIGH Voltage (Note 15) Output LOW Voltage (Note 15) Input HIGH Voltage (Single-Ended) CMOS PECL TTL Input LOW Voltage (Single-Ended) CMOS PECL TTL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 16) Input HIGH Current Input LOW Current 0.5 Min 90 3855 3055 3500 3775 2000 0 3055 0 3475 2.0 3575 Typ 110 3980 3180 Max 130 4105 3305 5000 5000 5000 1500 3375 800 3675 5.0 Min 90 3855 3055 3500 3775 2000 0 3055 0 3475 2.0 3575 25C Typ 110 3980 3180 Max 130 4105 3305 5000 5000 5000 1500 3375 800 3675 5.0 Min 95 3855 3055 3500 3775 2000 0 3055 0 3475 2.0 3575 85C Typ 115 3980 3180 Max 135 4105 3305 5000 5000 5000 1500 3375 800 3675 5.0 Unit mA mV mV mV
VIL
mV
VBB VIHCMR
mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 15. All loading with 50 W to VCC - 2.0 V. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 12. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 17)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 18) Output LOW Voltage (Note 18) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) Input HIGH Current Input LOW Current 0.5 Min 90 -1145 -1945 -1225 -1945 -1525 -1425 Typ 110 -1020 -1820 Max 130 -895 -1695 -880 -1625 -1325 0.0 Min 90 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 110 -1020 -1820 Max 130 -895 -1695 -880 -1625 -1325 0.0 Min 95 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 115 -1020 -1820 Max 135 -895 -1695 -880 -1625 -1325 0.0 Unit mA mV mV mV mV mV V
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC - 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP446, MC100EP446
Table 13. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
-40C Symbol fmax Characteristic Maximum Frequency (Figure 15) CKSEL High CKSEL Low tPLH, tPHL Propagation Delay to Output Differential CKSEL = 0 CLK TO SOUT, CLK TO PCLK CKSEL = 1 tS Setup Time D to CLK+ SYNC- to CLK- CKEN+ to CLK- Hold Time D to CLK+ SYNC- to CLK- CLK- to CKEN- CLK TO SOUT, CLK TO PCLK (Figure 4) (Figure 5) (Figure 6) (Figure 4) (Figure 6) 3.2 1.6 650 700 775 850 -375 200 70 -525 0 75 150 200 145 0.2 150 SOUT 50 800 100 <1 1200 150 150 70 3.4 1.7 750 800 875 950 -425 140 40 -575 45 850 900 975 1050 3.2 1.6 700 750 825 900 -400 200 70 -550 0 75 150 200 145 0.2 800 120 <1 1200 170 150 90 3.4 1.7 800 850 925 1000 -450 140 40 -600 45 900 950 1025 1100 3.2 1.6 725 775 875 950 -450 200 70 -600 0 75 150 200 145 0.2 800 140 <1 1200 190 3.4 1.7 850 900 1000 1075 -500 140 40 -650 45 ps 975 1025 1125 1200 Min Typ Max Min 25C Typ Max Min 85C Typ Max Unit
GHz
ps ps
ps
th
ps
tpw
Minimum Pulse Width (Note 22) Data (D0-D7) SYNC CKEN Random Clock Jitter (RMS) v fmax Typ Input Differential Voltage Swing (Note 21) Output Rise/Fall Times (20% - 80%)
tJITTER VPP tr tf
ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 21. VPP(min) is the minimum input swing for which AC parameters are guaranteed. 22. The minimum pulse width is valid only if the setup and hold times are respected.
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MC10EP446, MC100EP446
CLK
Data Setup Time
Data Valid ts th +0-
Figure 4. Setup and Hold Time for Data
SYNC SYNC
CLK
ts CLK CKEN CLK tS th
Figure 5. Setup Time for SYNC
Figure 6. Setup and Hold Time for CKEN
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MC10EP446, MC100EP446
APPLICATION INFORMATION The MC10/100EP446 is an integrated 8:1 parallel to serial converter. An attribute for EP446 is that the parallel inputs D0-D7 (Pins 17 - 24) can be configured to accept either CMOS, ECL, or TTL level signals by a combination of interconnects between VEF (Pin 27) and VCF (Pin 26) pins. For CMOS input levels, leave VEF and VCF open. For ECL operation, short VCF and VEF (Pins 26 and 27). For TTL operation, connect a 1.5 V supply reference to VCF and leave the VEF pin open. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 1.5 kW or 500 W between VCF and VEE for 3.3 V or 5.0 V power supplies, respectively. Note: all pins requiring ECL voltage inputs must have a 50 W terminating resistor to VTT (VTT = VCC - 2.0 V). The CKSEL input (Pin 2) is provided to enable the user to select the serial data rate output between internal clock data rate or twice the internal clock data rate. For CKSEL LOW operation, the time from when the parallel data is latched to when the data is seen on the SOUT is on the falling edge of the 7th clock cycle plus internal propagation delay (Figure 7). Note the PCLK switches on the falling edge of CLK.
A
CLK D0 D1 D2 D3 D4 D5 D6 D7
Number of Clock Cycles from Data Latch to SOUT 1 2 3 4 5 6 7
D0-1 D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 Data Latched
D0-2 D1-2 D2-2 D3-2 D4-2 D5-2 D6-2 D7-2 Data Latched D0-1
D0-3 D1-3 D2-3 D3-3 D4-3 D5-3 D6-3 D7-3 Data Latched D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1
D0-4 D1-4 D2-4 D3-4 D4-4 D5-4 D6-4 D7-4 Data Latched D0-2 D1-2 D2-2 D3-2 D4-2 D5-2 D6-2
SOUT CKSEL PCLK
A
Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW
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MC10EP446, MC100EP446
Similarly, for CKSEL HIGH operation, the time from when the parallel data is latched to when the data is seen on the SOUT is on the rising edge of the 14th clock cycle plus internal propagation delay (Figure 8). Furthermore, the PCLK switches on the rising edge of CLK. A
CLK D0 D1 D2 D3 D4 D5 D6 D7 Data Latched SOUT CKSEL PCLK D0-1 D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 Data Latched D0-1 D0-2 D1-2 D2-2 D3-2 D4-2 D5-2 D6-2 D7-2 Data Latched D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 D0-2 D0-3 D1-3 D2-3 D3-3 D4-3 D5-3 D6-3 D7-3 Number of Clock Cycles from Data Latch to SOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
Figure 8. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH
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D1-2
MC10EP446, MC100EP446
The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip-flops and clock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt serial data bits are generated. The falling edge of the SYNC followed by a falling edge of CLK initiates the start of the conversion process on the next rising edge of CLK (Figures 9 and 10). As shown in the figures below, the device will start to latch the parallel input data after the a falling edge of SYNC , followed by the falling edge CLK , on the next rising of edge of CLK (R) for CKSEL LOW
SYNC (Synchronous ENABLE) Number of Clock Cycles from Data Latch to SOUT SYNC (Asynchronous RESET) CLK SYNC D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7
A A
A
D0-1 D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 D0-2 D1-2 D2-2 D3-2 D4-2 D5-2 D6-2 D7-2 Data Latched D0-1 D1-1 D2-1 D3-1 D0-3 D1-3 D2-3 D3-3 D4-3 D5-3 D6-3 D7-3 Data Latched D4-1 D5-1 D6-1 D7-1 D0-2 D1-2 D2-2 D3-2 D0-4 D1-4 D2-4 D3-4 D4-4 D5-4 D6-4 D7-4 Data Latched D4-2 D5-2 D6-2
Data Latched
SOUT CKSEL PCLK
Figure 9. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC
SYNC
A
A
CLK
A
Figure 10. Synchronous Release of SYNC for CKSEL LOW
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MC10EP446, MC100EP446
For CKSEL HIGH, as shown in the timing diagrams below, the device will start to latch the parallel input data after the falling edge of SYNC , followed by the falling edge CLK , on the second rising edge of CLK (R) (Figures 11 and 12).
SYNC (Synchronous ENABLE) SYNC (Asynchronous RESET) CLK SYNC D0 D1 D2 D3 D4 D5 D6 D7 1
Number of Clock Cycles from Data Latch to SOUT 2 3 4 5 6 7 8 9 10 11 12 13 14
AA A
D0-1 D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 Data Latched D0-2 D1-2 D2-2 D3-2 D4-2 D5-2 D6-2 D7-2 Data Latched D0-1 D0-3 D1-3 D2-3 D3-3 D4-3 D5-3 D6-3 D7-3 Data Latched D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 D0-2 D1-2 D0-4 D1-4 D2-4 D3-4 D4-4 D5-4 D6-4 D7-4
SOUT CKSEL PCLK
Figure 11. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH and SYNC
SYNC
A
A CLK
A
Figure 12. Synchronous Release of SYNC for CKSEL HIGH
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MC10EP446, MC100EP446
The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the falling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resume all activities (Figure 13).
Internal Clock Disabled Internal Clock Enabled
CLK CKEN SOUT PCLK CKSEL D0-1 D1-1 D2-1 D3-1 D4-1 D5-1
Figure 13. Timing Diagram with CKEN with CKSEL HIGH
The differential PCLK output (Pins 14 and 15) is a word framer and can help the user synchronize the serial data output, SOUT (Pins 11 and 12), in their applications. Furthermore, PCLK can be used as a trigger for input parallel data (Figure 14). An internally generated voltage supply, the VBB pin, is available to this device only. For single-ended input
conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Also, both outputs of the differential pair must be terminated (50 W to VTT) even if only one output is used.
CLK RESET
CLK Pattern Generator Data Format Logic (FPGA, ASIC) PARALLEL DATA OUTPUT PARALLEL DATA INPUT
SYNC EP446
SOUT
SERIAL DATA
TRIGGER
PCLK
Figure 14. PCLK as Trigger Application
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MC10EP446, MC100EP446
800 CKSEL High 700 VOUTpp (mV) 600 500 400 300 200 100 0 CKSEL Low
0
500
1000
1500
2000
2500
3000
3500
INPUT CLOCK FREQUENCY (MHz)
Figure 15. Typical VOUTPP versus Input Clock Frequency, 255C
Figure 16. SOUT System Jitter Measurement (Condition: 3.4 GHz input frequency, CKSEL HIGH, BEOFE32 bit pattern on SOUT
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MC10EP446, MC100EP446
Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 17. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION
Device MC10EP446FA MC10EP446FAG MC10EP446FAR2 MC10EP446FAR2G MC100EP446FA MC100EP446FAG MC100EP446FAR2 MC100EP446FAR2G MC10EP446MNG MC100EP446MNG MC10EP446MNR4G MC100EP446MNR4G Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 74 Units / Rail 74 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EP446, MC100EP446
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE C
-T-, -U-, -Z- AE P V V1 DETAIL Y
BASE METAL
32
A1
A
25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U-
17
N 9 -Z- S
8X 4X
M_
R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD K Q_
GAUGE PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
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0.20 (0.008)
S1
0.20 (0.008) AC T-U Z
F
EE EE EE
9
D
M
AC T-U Z
DETAIL Y
AE
MC10EP446, MC100EP446
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
8
1
b 0.10 C A B
32 X
0.05 C BOTTOM VIEW
32 X
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE
TOP VIEW SIDE VIEW
9
PIN ONE LOCATION
E
(A3) A A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
D2
K
17 32 X
SOLDERING FOOTPRINT*
5.30 3.20 0.63
32 X
E2
24 32 25
e
3.20
5.30
0.28
0.50 PITCH
28 X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC10EP446/D

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